Smart Equipment Strategies Optimize Final Test


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Editor's Note: This article orginally appeared in the March 2012 issue of SMT Magazine.Falling IC Selling Prices Require the Highest Efficiency As a result of falling sales prices and reduced margins, all semiconductor companies need to focus even more on their cost structure. While this fast-growing portion of electronics for consumer applications is a great opportunity for the industry, none are willing to pay the high prices associated with the ICs used in automotive applications. Efficiency will become crucial.

With semiconductor production becoming more efficient and less costly, the relative areas of cost added by final test increases and becomes worth a closer look.Semiconductor Test Leveraging Moore’s Law

As semiconductors became more complex, Moore’s Second Law was formulated: The capital cost of a semiconductor fabrication also increases exponentially over time. This may have been true for some time, but testers have grown more intelligent, becoming beneficiaries of Moore’s Law themselves. Built-in components are becoming less expensive while offering higher performance. State-of-the-art automated test equipment (ATE) now offers enhanced capabilities and is becoming more cost-efficient compared to other test cell parts. Test cell configurations now exist in which testers are no longer the most expensive part.Test Cell Hardware Must Keep Pace--At a Reasonable Price Unfortunately, the performance profiles of the other parts of the test cell are better defined by mechanical and thermal issues. In this case, Moore’s Law is not applicable in the same way. Often, the hardware of test handling equipment causes a bottleneck. Typically, two requirements for test handlers exist:

  1. Test handlers must offer innovative technology to keep pace with new testers and cope with new semiconductor packages.
  2. Test handlers need to find ways to become more cost-efficient themselves, although they cannot participate in Moore’s Law due to their mechanical structure.

Figure 1: State-of-the-art test handler, the MT2168. Speed: Maximum Throughput The task for test handlers is to bring as many devices to the contact site as the tester can process to avoid idle times. From the tester perspective, it is either testing or waiting for new devices. From the handler’s viewpoint, several parallel processes are evident: While one set of packages keeps the contact site busy, the next set of untested packages needs to be received from the loading station and brought to test temperature. The tested packages of the previous set must be sorted and transported from the contact site to the respective unloading station. Although the overall speed of the handler is determined by both figures, depending on the application and its typical test time, either the index time for the device under test (DUT) exchange or the time for the transportation and sorting processes becomes more critical.Applications with Long Test TimesIn the case of long test times, there is enough time for the internal infrastructure of the handler to transport the packages. The critical issue is the time needed to replace the tested devices with new, untested devices at the contact site. Here, pick-and-place has an advantage, especially for multisite testing: The packages at all contact sites can be replaced simultaneously. Gravity has clear limitations that lead to significantly longer index times. Using gravity force only, the speed for the DUT exchange is given and cannot increase. Additionally, because of the design, multisite gravity handlers often are unable to completely exchange all DUTs simultaneously, but need two (or more) iterations.Applications with Short Test TimesFor ICs, which require short test times, the handler internal transportation speed is the pivotal feature. Even compared to the latest pick-and-place generation, gravity handlers have clear advantages. Today’s state-of-the-art pick-and-place mechanisms, based on the actual handling of each single package, cannot beat the gravity handling of multiple packages in tubes and tracks.When it comes to high parallel test, strip testing is the clear choice. Here the number of packages is no longer critical, as long as the maximum number of signal lines is not exceeded. Unfortunately, strip test forces the back-end process to be changed and eliminates final test as last process step because singulation must be performed after the strip test. The new concept of test-in-trays overcomes this, but requires additional investment loading and unloading equipment into/from the trays. Nevertheless, this is beneficial for true high-volume production.In traditional single-package tests, the number of simultaneously tested devices increases to 16 or even 32. For these configurations, the internal transportation’s speed and soak capacity of the test handler is again critical because more packages need to be presented to the tester simultaneously.Figure 2: A new approach—test-in carriers. Regardless of the type of high parallel test used, a sufficiently high contact force has to be available. Therefore, exceeding a certain number of devices tested simultaneously requires more than adding more contact sites. The overall architecture of the test handler must be reviewed.Comprehensive Approaches, Integrated Solutions The typical test cell used for IC final test consists of the tester, load board, socket and test handler, including a package-dedicated kit. For typical IC final test, clear standards for functionality and interfaces have been defined and are well established for each of these elements. This standardization has numerous advantages for matching test components from multiple suppliers. However, the sharply defined functions limit the potential optimized performance of the overall system. Each of the previously mentioned elements has clearly defined functions in the test setup for standard ICs. The supplier of each single element strives to optimize each element. Nevertheless, optimizing each single element and function will not necessarily provide optimized system performance and resulting test accuracy and yield. While such standardized, multi-vendor solutions may suffice for standard IC tests, more advanced applications, such as RF, fine-pitch, high pin count, MEMS, and extreme thermal test requirements cannot be adequately served, inflating total operating costs. Based on the approach of value engineering, the overall function-to-cost ratio needs to be critically analyzed. What function(s) does a single element fulfill? Can a function be transferred to another element to improve the overall performance and/or to lower overall cost? What compromises of standardized element design practices can be improved upon with system-level design?Additional Ratios to be Considered Simply comparing equipment purchasing prices is misleading. A more meaningful figure is the cost per tested device. This includes how many ICs pass the test cell before an operator has to intervene (MCBA)? How many test cells can be run by one operator? This is not only defined by the robustness and reliability of the machine, but also by the loading and unloading capacities of the handler. In addition to the pure utilization rate, i.e., the amount of time that the handler is really available for use in production, the reuse of equipment must not be neglected--it is standard for most test handling equipment to be able to be converted for other packages. From an organizational viewpoint, easy scalability from engineering site setup to a fully-automated, high-volume production setup offers significant advantages in terms of efficiency and cost.

Looking at the life cycle of the equipment, upgrades and optional features that can be retrofitted later also ensure that the original investment does not become obsolete.Downtimes: The Natural Enemy of Test Cell Efficiency In an ideal world, a system would run forever. In reality, equipment deployment leads to wear and contamination, which requires maintenance and parts replacement. Nevertheless, smart system maintenance, as well as an optimized spare part supply, can reduce unscheduled downtimes significantly. The most efficient maintenance includes well-defined preventive maintenance procedures and schedules, training opportunities for people onsite, and professional support in critical situations. In the case of an integrated solution at a test cell, the vendor can offer maintenance recommendations, e.g., how to harmonize handler maintenance and contact socket cleaning.Advanced handler features provide additional advantages. Some examples include automatic contact site cleaning and the ability to disable dedicated contact sites. For cold test, downtimes are even worse; however, innovative handler functionalities can offer substantial benefits. In-time availability of spare parts, smart programs and consultancy, as well as determining which spares to have onsite without creating endless inventory, cover the material side.Conclusion More than just hardware is purchased when buying a piece of test equipment. While software is considered a vital part of a tester’s features, classical “test cell hardware” (i.e., the test handler, the contactor, and the load board) involves more than just equipment. Smart, usable features make the test cell more efficient. Integrated approaches, turnkey solutions, and a thorough understanding of the overall test, as well as a responsive after-sales service that offers training, support, and spare parts supply, can lead to less cost and higher yields. In the end, it is not the capabilities and purchase price of the initial hardware that make the difference, but rather the yield per invested dollar over the overall life span, which can be optimized by various services and expert know how.

About the author: Barbara Loferer has been working in the semiconductor industry for more than 10 years. She has a master’s degree in business administration. Her current responsibilities include marketing and marketing communications for all Multitest product lines. Here she has published several articles and co-edited various papers about final test.

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