If you’ve been in the SMT industry for any length of time and involved in ordering stencils, you may have instructed your stencil supplier to design your stencil to "industry standards" or per IPC standards. These are very loose terms and may be interpreted differently by different stencil manufacturers. Many parts of the IPC-7525B standard are only recommendations, and the recommendations are typically a range of size reductions and/or area reductions for different types of components. In this column, I will discuss how our company interprets these guidelines and look at general design principles that should be applied to every stencil.
Four primary types of components should be addressed when designing SMT stencils:
- Pitch components
- Chip components
- Ball grid arrays (BGAs)
- Bottom-terminated components, including LEDs
1. Pitch Components
As I’ve said in previous columns, if you expect your stencil provider to design your stencils for optimum print performance, it is very important to supply them with the copper outer layers, paste layers, mask layers, and silkscreen layers. When pin-in-paste applications are required, or there are open vias in component thermal pads, it is also key that the drill layers are provided along with the board stackup, or at minimum, the overall board thickness.
If you are only supplying the paste layer, the stencil manufacturer has no idea if the paste layer has already been reduced and may apply additional reductions creating very poor print and solder results. If you ask your stencil supplier to cut the stencil per the supplied solder paste layer, the stencil supplier typically does not review the paste layout for optimal design. When industry-standard stencil designs are applied, adjusting the paste layer to match the outer copper layer is the best starting point. When doing this, the stencil design engineer must verify mask defined pads are identified and make sure the paste layer uses the mask layer to create the paste apertures for these components.
Pitch components can be described as any component with leads or land pads that repeat, such as QFPs, QFNs, resistor networks, some TSSOPs, etc. Stencil design is discussed in the current IPC-7525B standard. The standard says, “184.108.40.206 leaded SMDs for leaded SMDs (e.g., J-leaded or gull-wing components with pitch) the aperture size reduction is typically 0.03–0.08 mm [1.2–3.1 mils] in width and in length.” In general, a 2-mil reduction in width and length is recommended in the standard.
One issue I’ve seen through over the years is in many cases, PCB design may not be consistent. For instance, if a 0.5-mm (20-mil) pitch QFP has a copper land pad that is 14 mils wide, there would be a 6-mil gap between each copper pad. If a 2-mil reduction is made to the stencil aperture, the aperture would be 12 mils wide with a gap between each aperture of 8 mils. Eight-mil gaps and 12-mil apertures can result in bridging on these types of components, especially if there are no solder mask dams between land pads. When a specific reduction is defined, such as a 2-mil reduction, it does not take into consideration the varying designs applied to PCBs.
What I recommend instead of a defined reduction in width is what I refer to as the “half pitch rule.” This rule changes the aperture width to half of the pitch or 1:1 with copper—whichever is smaller and leaves the length the same as copper. If the pitch of the component is 0.5 mm, then the stencil aperture width should be 0.25mm or 9.8 mils wide. In many cases, stencil suppliers will refer to 0.5-mm pitch as 20-mil pitch parts and make the aperture 10 mils wide. The result is a 10-mil wide aperture with a 10-mil wide gap in between. This rule has been proven over time, and the only issue I’ve seen is when there are no solder mask dams between land pads. When this occurs, it is recommended to make an additional 1-mil reduction in aperture width. In the precious example, if there was no solder mask between land pads, a 9-mil wide aperture would be recommended with an 11-mil gap between.
2. Chip Components
The second type of components to be addressed when performing industry-standard stencil designs are chip components. When looking at stencil design for chip components, the first question to be addressed is will no-clean or water-soluble paste be used on the PCB assembly. For many customers, when no-clean paste is used, stencil design to reduce or eliminate solder balls or mid-chip beads is required. If water-soluble solder paste is used, many customers choose not to apply custom stencil designs to reduce solder balls and just apply an overall reduction per side or a percentage reduction.
Figure 4 shows the three primary designs used to reduce or eliminate solder balls or mid-chip beads for no-clean processes. All three designs reduce paste volume on the inside edge of the aperture. When customers ask me which I recommend, I recommend the U-shape or inverted homeplate. The reason is these designs remove paste from the center of the inside edges so that when the part is placed into the paste, paste is not "squeezed" out in the center, between the pads.
If you look at the standard homeplate design in Figure 4, it is easy to visualize when the part goes through reflow, the paste squeezed between the two pads will coalesce and work its way to the outside edge of the component creating a solder ball or mid-chip bead. These shapes are typically applied to 0402 components and larger; however, they can be applied to 0201 components based on the land pad layout if solder balls are a concern. In all cases, when these designs are applied, area ratios must be checked to make sure they are large enough to completely release solder paste. In general, area ratios on chip components with these no-clean designs should remain above 0.66.
BGAs are another category of components that must be addressed when designing stencils. IPC-7525B recommends a 2-mil reduction in size for plastic BGAs, specifically calculated volumes for ceramic BGAs, and a 1:1 design or 1-mil reduction for micro-BGAs. Normally, at the stencil design process, the stencil design engineer does not know the type of BGA as the BOM is typically not supplied and time does not allow for this type of review to be assessed.
When customers ask us to design their stencils based on industry-standard designs, we recommend looking at the size of the copper or mask defined land pad. If the land pad is larger than 19.7 mils, a 1–2-mil reduction is applied, and the pad is left round. When designing stencils for micro-BGAs where the copper or mask defined land pads are less than 19.7 mils, industry standards typically recommend leaving the aperture 1:1 with the copper pad and changes the aperture shape from round to square with a corner radius. This rounded square aperture design enlarges the solder paste deposit, increases the area ratio, and adds solder paste volume in the corners of the round land pads without decreasing the gap between land pads that can cause shorts or bridges. Printing on the mask for these types of components creates a better stencil to PCB gasket resulting in better solder paste transferred from the stencil down into the cavity created by the mask surrounding the BGA land pads.
4. Bottom-terminated components
Parts in this category include QFNs, LGAs, and LEDs. Bottom-terminated components with perimeter leads should be designed using the half pitch rule. Thermal pads on QFN and DFN type components typically create two challenges. First, if too much volume is applied to the thermal pad, skew or twist can occur during reflow. When the solder paste goes liquid, in the case of excess volume, the part will float and twist, causing the perimeter leads to bridge. IPC-7525B recommends a 20–50% reduction in volume for QFN and DFN thermal pads. Industry-standard designs typically recommend a 40% reduction in volume using a window-pane design. LEDs require similar volume reductions to prevent skewing and shifting.
The second challenge these components present is voiding. The window-pane design also creates channels for volatiles to escape as the solder paste goes liquid during reflow. If these volatiles are not allowed to escape, they can become trapped, creating large voids.
Over the years, many different stencil design patterns have been tested for void reduction, and to date, these different design patterns have not shown better results. The industry continues to use the window-pane design for BTC thermal pads. In my experience, the best approach to void reduction is to evaluate the stencil design, specific solder paste being used, and the oven profile together to optimize the process for the specific PCB being assembled. In many cases, land pads for LGAs are both copper and mask defined. It is critical this is recognized during the stencil design process.
Typically, the shape guidelines used for BGAs can be used for these components as well. When the round land pads are less than 19.7 mils, it is recommended to use a square pad with a radius on the corners. When larger rectangular pads are used, in some cases, a “web” can be created in the center of the land pad to allow volatiles to escape as paste goes liquid and gasses form. By doing this, voiding can be reduced on these pads.
Finally, when designing stencil apertures to print LEDs, a reduction in volume versus the copper land pad must be made. This reduction is usually in the 30–50% range depending on the specific LED. The reduction prevents the component from rotating or skewing during reflow and also prevents the part from pulling to one of the two sides. The web in the center of the apertures also create an avenue for volatiles to escape as the paste goes thru the reflow process.
Overall, these are the primary component types that should be addressed during each stencil design review. Other components not discussed in this column would typically receive a small reduction to reduce the possibility of creating solder balls during reflow. These basic design rules will produce good print results for most PCB assemblies. I believe it is key for the PCB manufacturer to understand their stencil supplier’s design guidelines so that when yield challenges occur, they can dial those in to improve the overall yield of their assemblies. Of course, there are always exceptions for specific challenges, and these are usually handled after the initial boards are assembled.
In my next column, I will address root-cause stencil design for specific challenges, such as tombstones and insufficient volume at print and after reflow.
Greg Smith is manager of stencil technology at BlueRing Stencils.